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ICS9ERS3165 idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 embed ded 64-pin industrial t emper a tur e range ck505 compatible clock 1 da t asheet pin configuration recommended application:industrial temperature ck505 compatible clock for embedded systems output features: ? 2 - cpu differential low power push-pull pairs ? 9 - src differential low power push-pull pairs ? 1 - cpu/src selectable differential low power push-pullpair ? 1 - src/dot selectable differential low power push-pullpair ? 5 - pci, 33mhz ? 1 - pci_f , 33mhz free r unning ? 1 - usb, 48mhz ? 1 - ref , 14.318mhz key specifications:? cpu outputs cycle-cycle jitter < 85ps ? src output cycle-cycle jitter < 125ps ? pci outputs cycle-cycle jitter < 250ps ? +/- 100ppm frequency accuracy on cpu & src clocks features/benefits:? does not require external pass transistor for voltageregulator ? integrated 33ohm series resistors on differential outputs,z o =50 ? supports spread spectrum modulation, default is 0.5%down spread ? uses external 14.318mhz crystal, external crystal loadcaps are required for frequency tuning ? selectable between one src differential push-pull pairand two single-ended outputs ? meets pciex gen2 specification on dedicated srcoutputs. muxed src outputs meet pciex gen1 specification, except src1. ? meets pciex <85ps cycle-tocycle jitter for src[11:1] ? single-ended programmable slew rate control for rfireduction pci0/cr#_a 1 64 sclk vddpci 2 63 sdata pci1/cr#_b 3 62 ref/fslc/test_sel pci2/tme 4 61 vddref pci3 5 60 x1 pci4/27_sel 6 59 x2 pci5_f/itp_en 7 58 gndref gndpci 8 57 fslb/test_mode vdd48 9 56 ck_pwrgd/pd# usb48m/fsla 10 55 vddcpu gnd48 11 54 cput_lr0 vddi/o96mhz 12 53 cpuc_lr0 dot96t/srct_lr0 13 52 gndcpu dot96c/srcc_lr0 14 51 cput_f_lr1 gnd 15 50 cpuc_f_lr1 vdd 16 49 vddcpu_io 27fix/lcdt/srct_lr1/se1 17 48 nc 27ss/lcdc/srcc_lr1/se2 18 47 cput_itp_lr2/srct8 gnd 19 46 cpuc_itp_lr2/srcc8 vddpll3i/o 20 45 vddsrci/o srct_lr2/sataclkt 21 44 srct_lr7/cr#_f srcc_lr2/sataclkc 22 43 srcc_lr7/cr#_e gndsrc 23 42 gndsrc srct_lr3/cr#_c 24 41 srct_lr6 srcc_lr3/cr#_d 25 40 srcc_lr6 vddsrci/o 26 39 vddsrc srct_lr4 27 38 pci_stop# srcc_lr4 28 37 cpu_stop# gndsrc 29 36 vddsrci/o srct_lr9 30 35 srcc_lr10 srcc_lr9 31 34 srct_lr10 srcc_lr11/cr#_g 32 33 srct_lr11/cr#_h 64-tssop ICS9ERS3165 27_sel pin13 pin14 0 (b1b7=1) dot96t dot96c 1 (b1b7=0) srct_lr0 srcc_lr0 27_sel pin17 pin18 0 lcdt_ss lcdc_ss 1 27fix 27ss note : pin 17/18 defaults to a different spread domain than src without bios intervention. all pin numbers aref or tssop pac kage b ut apply to corresponding signals on mlf as well. fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz usb mhz dot mhz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 1 1 1 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common outpu t parameters table for correct values. table 1: cpu frequency select table 96.00 100.00 33.33 14.318 48.00 reserved
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 2 tssop pin description pin# pin name type description 1 pci0/cr#_a i/o 3.3v pci clock output or clock request control a fo r either src0 or src2 pair the power-up default is pci0 output, but this pin m ay also be used as a clock request control of src pair 0 or src pair 2 via smb us. before configuring this pin as a clock request pin, the pci output must fir st be disabled in byte 2, bit 0 of smbus address space . after the pci output is di sabled (high-z), the pin can then be set to serve as a clock request pin for eit her src pair 2 or pair 0 using the cr#_a_en bit located in byte 5 of smbus address space. byte 5, bit 7 0 = pci0 enabled (default) 1= cr#_a enabled. byte 5, bit 6 controls whether cr#_a controls src0 or src2 pair byte 5, bit 6 0 = cr#_a controls src0 pair (default), 1= cr#_a controls src2 pair 2 vddpci pwr power supply pin for the pci outputs, 3.3v nomin al 3 pci1/cr#_b i/o 3.3v pci clock output/clock request control b for e ither src1 or src4 pair the power-up default is pci1 output, but this pin m ay also be used as a clock request control of src pair 1 or src pair 4 via smb us. before configuring this pin as a clock request pin, the pci output must fir st be disabled in byte 2, bit 1 of smbus address space . after the pci output is di sabled (high-z), the pin can then be set to serve as a clock request pin for eit her src pair 1 or pair 4 using the cr#_b_en bit located in byte 5 of smbus address space. byte 5, bit 5 0 = pci1 enabled (default) 1= cr#_b enabled. byte 5, bit 4 controls whether cr#_b controls src1 or src4 pair byte 5, bit 4 0 = cr#_b controls src1 pair (default) 1= cr#_b controls src4 pair 4 pci2/tme i/o 3.3v pci clock output / trusted mode enable (tme) l atched input. this pin is sampled on power-up as follows 0 = overclocking of cpu and src allowed 1 = overclocking of cpu and src not allowed after being sampled on power-up, this pin becomes a 3.3v pci output 5 pci3 out 3.3v pci clock output. 6 pci4/27_sel i/o 3.3v pci clock output / 27mh mode select for pin17, 18 strap. on powerup, the logic value on this pin determines the power-up def ault of dot_96/src0 and 27mhz/src1 output and the function table for the pi n17 and pin18. 7 pci5_f/itp_en i/o free running pci clock output and itp/src8 enable s trap. this output is not affected by the state of the pci_stop# pin. on powe rup, the state of this pin determines whether pins 46 and 47 are an itp or src pair. 0 =src8/src8# 1 = itp/itp# 8 gndpci pwr ground for pci clocks. 9 vdd48 pwr power supply for usb clock, nominal 3.3v. 10 usb48m/fsla i/o fixed 48mhz usb clock output. 3.3v./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristic s for vil_fs and vih_fs values. 11 gnd48 pwr ground pin for the 48mhz outputs. 12 vddi/o96mhz pwr 1.05v to 3.3v from external power supply 13 dot96t/srct_lr0 out true clock of src or dot96. the power-up default fu nction depends on 27_select,1= src0, 0=dot96 14 dot96c/srcc_lr0 out complement clock of src or dot96. the power-up defa ult function depends on 27_select,1= src0, 0=dot96 15 gnd pwr ground pin for the dot96 clocks. 16 vdd pwr power supply for src / se1 and se2 clocks, 3.3v nominal.
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 3 tssop pin description (continued) pin # pin name type description 17 27fix/lcdt/srct_lr1/se1 out single-ended 3.3v 27mhz fix clock output / true clo ck of differential src1 or lcd clock pair / single ended 3.3v peripheral clock out put. the default output selection is determined by the sel_27 default latch value. s ee below: 27_sel=0 : lcd100 with -0.5% down spread is selected as def ault. lcd100 spread percentage can be adjusted or output can be changed to src or 3.3v single-ended peripheral clock output via smbus b1b[4:1]. 27_sel=1 : single-ended 27fix output is selected. 18 27ss/lcdc/srcc_lr1/se2 out single-ended 3.3v 27mhz fix clock output / compleme ntary clock of differential src1 or lcd clock pair / single ended 3.3v peripher al clock output. the default output selection is determined by the sel_27 defaul t latch value. see below: 27_sel=0 : lcd100 with -0.5% down spread is selected as def ault. lcd100 spread percentage can be adjusted or output can be changed to src or 3.3v single-ended peripheral clock output via smbus b1b[4:1]. 27_sel=1 : single-ended 27ss output is selected with -0.5% down spread as default. spread percentage can be adjusted via smb us b1b[4:1]. 19 gnd pwr ground pin for src / se1 and se2 clocks, pll3. 20 vddpll3i/o pwr 1.05v to 3.3v from external power supply 21 srct_lr2/sataclkt out true clock of differential src/sata clock pair. 22 srcc_lr2/sataclkc out complement clock of differential src/sata clock pai r. 23 gndsrc pwr ground pin for src clocks. 24 srct_lr3/cr#_c i/o true clock of differential src clock pair/ clock r equest control c for either src0 or src2 pair the power-up default is srcclk3 output, but this pi n may also be used as a clock request control of src pair 0 or src pair 2 via smb us. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disa bled, the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_c_en bit located in byte 5 of smbus address space. byte 5, bit 3 0 = src3 enabled (default) 1= cr#_c enabled. byte 5, bit 2 controls whether cr#_c controls src0 or src2 pair byte 5, bit 2 0 = cr#_c controls src0 pair (default), 1= cr#_c controls src2 pair 25 srcc_lr3/cr#_d i/o complementary clock of differential src clock pair/ clock request control d for either src1 or src4 pair the power-up default is srcclk3 output, but this pi n may also be used as a clock request control of src pair 1 or src pair 4 via smb us. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disa bled, the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_d_en bit located in byte 5 of smbus address space. byte 5, bit 1 0 = src3 enabled (default) 1= cr#_d enabled. byte 5, bit 0 controls whether cr#_d controls src1 or src4 pair byte 5, bit 0 0 = cr#_d controls src1 pair (default), 1= cr#_d controls src4 pair 26 vddsrci/o pwr 1.05v to 3.3v from external power supply 27 srct_lr4 i/o true clock of differential src clock pair 4 28 srcc_lr4 i/o complement clock of differential src clock pair 4 29 gndsrc pwr ground pin for src clocks. 30 srct_lr9 out true clock of differential src clock pair. 31 srcc_lr9 out complement clock of differential src clock pair. 32 srcc_lr11/cr#_g i/o src11 complement /clock request control for src9 p air the power-up default is src11#, but this pin may al so be used as a clock request control of src9 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src9 pair using byte 6, bit 5 of smbus configuration space byte 6, bit 5 0 = src11# enabled (default) 1= cr#_g controls src9
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 4 tssop pin description (continued) pin # pin name type description 33 srct_lr11/cr#_h i/o src11 true or clock request control h for src10 pai r the power-up default is src11, but this pin may als o be used as a clock request control of src10 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src10 pair using byte 6, bit 4 of smbus configuration space byte 6, bit 4 0 = src11 enabled (default) 1= cr#_h controls src10. 34 srct_lr10 out true clock of differential src clock pair. 35 srcc_lr10 out complement clock of differential src clock pair. 36 vddsrci/o pwr 1.05v to 3.3v from external power supply 37 cpu_stop# in stops all cpu clocks, except those set to be free r unning clocks. in amt mode 3 bits are shifted in from the ich to set the fsc, fs b, fsa values 38 pci_stop# in stops all pci clocks, except those set to be free r unning clocks. in amt mode 3 bits are shifted in from the ich to set the fsc, fsb, fs a values 39 vddsrc pwr vdd pin for src pre-drivers, 3.3v nominal 40 srcc_lr6 out complement clock of low power differential src cloc k pair. 41 srct_lr6 out true clock of low power differential src clock pair . 42 gndsrc pwr ground for src clocks 43 srcc_lr7/cr#_e i/o src7 complement or clock request control e for src6 pair the power-up default is src7#, but this pin may als o be used as a clock request control of src6 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space . after the src output is disabled (high-z), the pi n can then be set to serve as a clock request for src6 pair using byte 6, bit 7 of smbus configuration space byte 6, bit 7 0 = src7# enabled (default) 1= cr#_e controls src6. 44 srct_lr7/cr#_f i/o src7 true or clock request control 8 for src8 pair the power-up default is src7, but this pin may also be used as a clock request control of src8 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src8 pair using byte 6, bit 6 of smbus configuration space byte 6, bit 6 0 = src7# enabled (default) 1 = cr#_f controls src8. 45 vddsrci/o pwr 1.05v to 3.3v from external power supply 46 cpuc_itp_lr2/srcc8 out complement clock of low power differential cpu2/com plement clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows : pin 7 latched input value 0 = src8# 1 = itp# 47 cput_itp_lr2/srct8 out true clock of low power differential cpu2/true cloc k of differential src pair. the function of this pin is determined by the latched i nput value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8 1 = itp 48 nc n/a no connect 49 vddcpu_io pwr 1.05v to 3.3v from external power supply 50 cpuc_f_lr1 out complement clock of low power differenatial cpu clo ck pair. this clock will be free- running during iamt. 51 cput_f_lr1 out true clock of low power differential cpu clock pair . this clock will be free-running during iamt. 52 gndcpu pwr ground pin for cpu outputs 53 cpuc_lr0 out complement clock of low power differential cpu cloc k pair. 54 cput_lr0 out true clock of low power differential cpu clock pair . 55 vddcpu pwr power supply 3.3v nominal. 56 ck_pwrgd/pd# in notifies ck505 to sample latched inputs, or iamt entry/exit, or pwrdwn# mode 57 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. r efer to input electrical characteristics for vil_fs and vih_fs values. test_ mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 58 gndref pwr ground pin for crystal oscillator circuit 59 x2 out crystal output, nominally 14.318mhz. 60 x1 in crystal input, nominally 14.318mhz. 61 vddref pwr power pin for the ref outputs, 3.3v nominal. 62 ref/fslc/test_sel i/o 3.3v 14.318mhz reference clock/3.3v tolerant low th reshold input for cpu frequency selection. refer to input electrical characteristic s for vil_fs and vih_fs values/ test_sel: 3-level latched input to enable test mode . refer to test clarification table. 63 sdata i/o data pin for smbus circuitry, 5v tolerant. 64 sclk in clock pin of smbus circuitry, 5v tolerant.
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 5 pin configuration 64-pin mlf fslb/test_mode ck_pwrgd/pd# vddcpu cput_lr0 cpuc_lr0 gndcpu cput_f_lr1 cpuc_f_lr1 vddcpu_io nc cput_itp_lr2/srct8 cpuc_itp_lr2/srcc8 vddsrci/o srct_lr7/cr#_f srcc_lr7/cr#_e gndsrc 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 gndref 1 48 srct_lr6 x2 2 47 srcc_lr6 x1 3 46 vddsrc vddref 4 45 pci_stop# ref/fslc/test_sel 5 44 cpu_stop# sdata 6 43 vddsrc_io sclk 7 42 srcc_lr10 pci0/cr#_a 8 41 srct_lr10 vddpci 9 40 srct_lr11/cr#_h pci1/cr#_b 10 39 srcc_lr11/cr#_g pci2/tme 11 38 srcc_lr9 pci3 12 37 srct_lr9 pci4/27_sel 13 36 gndsrc pci5_f/itp_en 14 35 srcc_lr4 gndpci 15 34 srct_lr4 vdd48 16 33 vddsrci/o 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 usb48m/fsla gnd48 vddi/096mhz dot96t/srct_lr0 dot96c/srcc_lr0 gnd vdd 27fix/lcdt/srct_lr1/se1 27ss/lcdc/srcc_lr1/se2 gnd vddpll3i/o srct_lr2/sataclkt srcc_lr2/sataclkc gndsrc srct_lr3/cr#_c srcc_lr3/cr#_d ICS9ERS3165
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 6 mlf pin description pin# pin name type description 1 gndref pwr ground pin for crystal oscillator circuit 2 x2 out crystal output, nominally 14.318mhz. 3 x1 in crystal input, nominally 14.318mhz. 4 vddref pwr power pin for the ref outputs, 3.3v nominal. 5 ref/fslc/test_sel i/o 3.3v 14.318mhz reference clock/3.3v tolerant low th reshold input for cpu frequency selection. refer to input electrical characteristic s for vil_fs and vih_fs values/ test_sel: 3-level latched input to enable test mode . refer to test clarification table. 6 sdata i/o data pin for smbus circuitry, 5v tolerant. 7 sclk in clock pin of smbus circuitry, 5v tolerant. 8 pci0/cr#_a i/o 3.3v pci clock output or clock request control a fo r either src0 or src2 pair the power-up default is pci0 output, but this pin m ay also be used as a clock request control of src pair 0 or src pair 2 via smb us. before configuring this pin as a clock request pin, the pci output must first b e disabled in byte 2, bit 0 of smbus address space . after the pci output is disab led (high-z), the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_a_en bit located in byte 5 of smbus address spa ce. byte 5, bit 7 0 = pci0 enabled (default) 1= cr#_a enabled. byte 5, bit 6 controls whether cr#_a controls src0 or src2 pair byte 5, bit 6 0 = cr#_a controls src0 pair (default), 1= cr#_a controls src2 pair 9 vddpci pwr power supply pin for the pci outputs, 3.3v nomin al 10 pci1/cr#_b i/o 3.3v pci clock output/clock request control b for e ither src1 or src4 pair the power-up default is pci1 output, but this pin m ay also be used as a clock request control of src pair 1 or src pair 4 via smb us. before configuring this pin as a clock request pin, the pci output must first b e disabled in byte 2, bit 1 of smbus address space . after the pci output is disab led (high-z), the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_b_en bit located in byte 5 of smbus address spa ce. byte 5, bit 5 0 = pci1 enabled (default) 1= cr#_b enabled. byte 5, bit 4 controls whether cr#_b controls src1 or src4 pair byte 5, bit 4 0 = cr#_b controls src1 pair (default) 1= cr#_b controls src4 pair 11 pci2/tme i/o 3.3v pci clock output / trusted mode enable (tme) l atched input. this pin is sampled on power-up as follows 0 = overclocking of cpu and src allowed 1 = overclocking of cpu and src not allowed after being sampled on power-up, this pin becomes a 3.3v pci output 12 pci3 out 3.3v pci clock output. 13 pci4/27_sel i/o 3.3v pci clock output / 27mh mode select for pin24, 25 strap. on powerup, the logic value on this pin determines the power-up default o f dot_96/src0 and 27mhz/src1 output and the function table for the pi n24 and pin25. 14 pci5_f/itp_en i/o free running pci clock output and itp/src8 enable s trap. this output is not affected by the state of the pci_stop# pin. on powe rup, the state of this pin determines whether pins 53 and 54 are an itp or src pair. 0 =src8/src8# 1 = itp/itp# 15 gndpci pwr ground for pci clocks. 16 vdd48 pwr power supply for usb clock, nominal 3.3v. 17 usb48m/fsla i/o fixed 48mhz usb clock output. 3.3v./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristic s for vil_fs and vih_fs values. 18 gnd48 pwr ground pin for the 48mhz outputs. 19 vddi/o96mhz pwr 1.05v to 3.3v from external power supply 20 dot96t/srct_lr0 out true clock of src or dot96. the power-up default fu nction depends on 27_select,1= src0, 0=dot96 21 dot96c/srcc_lr0 out complement clock of src or dot96. the power-up defa ult function depends on 27_select,1= src0, 0=dot96 22 gnd pwr ground pin for the dot96 clocks. 23 vdd pwr power supply for src / se1 and se2 clocks, 3.3v nominal.
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 7 mlf pin description (continued) pin # pin name type description 24 27fix/lcdt/srct_lr1/se1 out single-ended 3.3v 27mhz fix clock output / true clo ck of differential src1 or lcd clock pair / single ended 3.3v peripheral clock out put. the default output selection is determined by the sel_27 default latch value. s ee below: 27_sel=0 : lcd100 with -0.5% down spread is selected as def ault. lcd100 spread percentage can be adjusted or output can be changed to src or 3.3v single-ended peripheral clock output via smbus b1b[4:1]. 27_sel=1 : single-ended 27fix output is selected. 25 27ss/lcdc/srcc_lr1/se2 out single-ended 3.3v 27mhz fix clock output / compleme ntary clock of differential src1 or lcd clock pair / single ended 3.3v peripher al clock output. the default output selection is determined by the sel_27 defaul t latch value. see below: 27_sel=0 : lcd100 with -0.5% down spread is selected as def ault. lcd100 spread percentage can be adjusted or output can be changed to src or 3.3v single-ended peripheral clock output via smbus b1b[4:1]. 27_sel=1 : single-ended 27ss output is selected with -0.5% down spread as default. spread percentage can be adjusted via smb us b1b[4:1]. 26 gnd pwr ground pin for src / se1 and se2 clocks, pll3. 27 vddpll3i/o pwr 1.05v to 3.3v from external power supply 28 srct_lr2/sataclkt out true clock of differential src/sata clock pair. 29 srcc_lr2/sataclkc out complement clock of differential src/sata clock pai r. 30 gndsrc pwr ground pin for src clocks. 31 srct_lr3/cr#_c i/o true clock of differential src clock pair/ clock r equest control c for either src0 or src2 pair the power-up default is srcclk3 output, but this pi n may also be used as a clock request control of src pair 0 or src pair 2 via smb us. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disa bled, the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_c_en bit located in byte 5 of smbus address space. byte 5, bit 3 0 = src3 enabled (default) 1= cr#_c enabled. byte 5, bit 2 controls whether cr#_c controls src0 or src2 pair byte 5, bit 2 0 = cr#_c controls src0 pair (default), 1= cr#_c controls src2 pair 32 srcc_lr3/cr#_d i/o complementary clock of differential src clock pair/ clock request control d for either src1 or src4 pair the power-up default is srcclk3 output, but this pi n may also be used as a clock request control of src pair 1 or src pair 4 via smb us. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disa bled, the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_d_en bit located in byte 5 of smbus address space. byte 5, bit 1 0 = src3 enabled (default) 1= cr#_d enabled. byte 5, bit 0 controls whether cr#_d controls src1 or src4 pair byte 5, bit 0 0 = cr#_d controls src1 pair (default), 1= cr#_d controls src4 pair 33 vddsrci/o pwr 1.05v to 3.3v from external power supply 34 srct_lr4 i/o true clock of differential src clock pair 4 35 srcc_lr4 i/o complement clock of differential src clock pair 4 36 gndsrc pwr ground pin for src clocks. 37 srct_lr9 out true clock of differential src clock pair. 38 srcc_lr9 out complement clock of differential src clock pair. 39 srcc_lr11/cr#_g i/o src11 complement /clock request control for src9 p air the power-up default is src11#, but this pin may al so be used as a clock request control of src9 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src9 pair using byte 6, bit 5 of smbus configuration space byte 6, bit 5 0 = src11# enabled (default) 1= cr#_g controls src9
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 8 mlf pin description (continued) pin # pin name type description 40 srct_lr11/cr#_h i/o src11 true or clock request control h for src10 pai r the power-up default is src11, but this pin may als o be used as a clock request control of src10 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src10 pair using byte 6, bit 4 of smbus configuration space byte 6, bit 4 0 = src11 enabled (default) 1= cr#_h controls src10. 41 srct_lr10 out true clock of differential src clock pair. 42 srcc_lr10 out complement clock of differential src clock pair. 43 vddsrci/o pwr 1.05v to 3.3v from external power supply 44 cpu_stop# in stops all cpu clocks, except those set to be free r unning clocks. in amt mode 3 bits are shifted in from the ich to set the fsc, fs b, fsa values 45 pci_stop# in stops all pci clocks, except those set to be free r unning clocks. in amt mode 3 bits are shifted in from the ich to set the fsc, fsb, fs a values 46 vddsrc pwr vdd pin for src pre-drivers, 3.3v nominal 47 srcc_lr6 out complement clock of low power differential src cloc k pair. 48 srct_lr6 out true clock of low power differential src clock pair . 49 gndsrc pwr ground for src clocks 50 srcc_lr7/cr#_e i/o src7 complement or clock request control e for src6 pair the power-up default is src7#, but this pin may als o be used as a clock request control of src6 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space . after the src output is disabled (high-z), the pi n can then be set to serve as a clock request for src6 pair using byte 6, bit 7 of smbus configuration space byte 6, bit 7 0 = src7# enabled (default) 1= cr#_e controls src6. 51 srct_lr7/cr#_f i/o src7 true or clock request control 8 for src8 pair the power-up default is src7, but this pin may also be used as a clock request control of src8 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src8 pair using byte 6, bit 6 of smbus configuration space byte 6, bit 6 0 = src7# enabled (default) 1 = cr#_f controls src8. 52 vddsrci/o pwr 1.05v to 3.3v from external power supply 53 cpuc_itp_lr2/srcc8 out complement clock of low power differential cpu2/com plement clock of differential src pair. the function of this pin is determined by the latched input value on pin 14, pcif5/itp_en on powerup. the function is as follows : pin 14 latched input value 0 = src8# 1 = itp# 54 cput_itp_lr2/srct8 out true clock of low power differential cpu2/true cloc k of differential src pair. the function of this pin is determined by the latched i nput value on pin 14, pcif5/itp_en on powerup. the function is as follows: pin 14 latched input value 0 = src8 1 = itp 55 nc n/a no connect 56 vddcpu_io pwr 1.05v to 3.3v from external power supply 57 cpuc_f_lr1 out complement clock of low power differenatial cpu clo ck pair. this clock will be free- running during iamt. 58 cput_f_lr1 out true clock of low power differential cpu clock pair . this clock will be free-running during iamt. 59 gndcpu pwr ground pin for cpu outputs 60 cpuc_lr0 out complement clock of low power differential cpu cloc k pair. 61 cput_lr0 out true clock of low power differential cpu clock pair . 62 vddcpu pwr power supply 3.3v nominal. 63 ck_pwrgd/pd# in notifies ck505 to sample latched inputs, or iamt entry/exit, or pwrdwn# mode 64 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. r efer to input electrical characteristics for vil_fs and vih_fs values. test_ mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table.
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 9 general descriptionbloc k dia gram po wer gr oups ICS9ERS3165 f ollo ws intel ck505 y ello w co v er specification. this cloc k synthesiz er pro vides a single chip solution f or intel processors and intel based systems. ICS9ERS3165 is driven with a 14.318mhz crystal. it also provides a tight ppm accuracy output f or ser ial a t a and pci-express suppor t. se1 lcd src1 pci ss pll2 ss pll5 fix pll3 cpuclk(1:0) pciclk 48mhz src2/sata xtal src8/cpu2_itp src(11:9),(7:6),(4:3) 27ss, se1, se2, lcd/src1 src0/ dot96m refclk dot_96m 27ss - se2 sata pciclk src8 cpuclk ss pll1 10 01 10 01 10 b1b7 itp_en b0 bit1 b1bit0 b0bit2 27_sel c o u t _ d i v c o u t _ d i v c o u t _ d i v 01 src2 s r c sata 48mhz src0 s r c src_main 27fix c o u t _ d i v vdd gnd 2 8 pciclk 9 11 usb 48 & core, fix pll analog/digital 12 15 dot96 output 16 19 27fix, 27ss, lcd, se outputs & core, 27ss/lcd/s e plll analog/digital 20 19 src1 output 26,36,45 29,42 all src outputs except src1 39 23 sata output, fix pll analog/digital 39 29,42 src outputs, cpu/pciex pll analog/digital 49 52 cpu outputs 55 52 cpu outputs & core 61 58 crystal, ref output & core description tssop pin number vdd gnd 9 15 pciclk 16 18 usb 48 & core, fix pll analog/digital 19 22 dot96 output 23 26 27fix, 27ss, lcd, se outputs & core, 27ss/lcd/s e plll analog/digital 27 26 src1 output 33,43,52 36,49 all src outputs except src1 46 30 sata output, fix pll analog/digital 46 36,49 src outputs, cpu/pciex pll analog/digital 56 59 cpu outputs 62 59 cpu outputs & core 4 1 crystal, ref output & core mlf pin number description
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 10 absolute maximum ratings parameter symbol conditions min max units notes maximum supply voltage vddxxx supply voltage 4.6 v 1,7 maximum supply voltage vddxxx_io low-voltage differen tial i/o supply 3.8 v 1,7 maximum input voltage v ih 3.3v lvcmos inputs 4.6 v 1,7,8 minimum input voltage v il any input gnd - 0.5 v 1,7 storage temperature ts - -65 150 c 1,7 case temperature tcase 115 c 1 input esd protection esd prot human body model 2000 v 1, 7 electrical characteristics - input/supply/common ou tput parameters parameter symbol conditions min typical max units notes ambient operating temp tambient - -40 85 c 1 supply voltage vddxxx supply voltage 3.135 3.465 v 1 supply voltage vddxxx_io low-voltage differential i/o supply 1 3.465 v 1 input high voltage v ihse single-ended inputs 2 v dd + 0.3 v 1 input low voltage v ilse single-ended inputs v ss - 0.3 0.8 v 1 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input leakage current i inres inputs with pull or pull down resistors v in = v dd , v in = gnd -200 200 ua 1 output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v olse single-ended outputs, i ol = 1 ma 0.4 v 1 output high voltage v ohdif differential outputs 0.7 0.9 v 1 output low voltage v oldif differential outputs 0.4 v 1 low threshold input- high voltage (test mode) v ih_fs_test 3.3 v +/-5% 2 v dd + 0.3 v 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 1.5 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 i dd_default 3.3v supply, pll1,2 off 95 125 ma 1 i dd_pll3dif 3.3v supply, pll1,2 differential out 106 125 ma 1 i dd_pll3se 3.3v supply, pll1,2 single-ended out 101 125 ma 1 i dd_io 0.8v supply, differential io current, all outputs enabled 25 32 50 ma 1 i dd_pd3.3 3.3v supply, power down mode 26 30 ma 1 i dd_pdio 0.8v io supply, power down mode 0.23 0.5 ma 1 i dd_iamt3.3 3.3v supply, iamt mode 47 60 ma 1 i dd_iamt0.8 0.8v io supply, iamtmode 5 10 ma 1 input frequency f i v dd = 3.3 v 14.318 mhz 2 pin inductance l pin 7 nh 1 c in logic inputs 1.5 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 operating supply current power down current iamt mode current input capacitance
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 11 electrical characteristics - smbus interface parameter symbol conditions min max units notes smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v olsmb @ i pullup 0.4 v 1 current sinking at v olsmb = 0.4 v i pullup smb data pin 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 maximum smbus operating frequency f smbus block mode 100 khz 1 ac electrical characteristics - input/common parame ters parameter symbol conditions min max units notes clk stabilization t stab from vdd power-up or de- assertion of pd# to 1st clock 1.8 ms 1 tdrive_src t drsrc src output enable after pci_stop# de-assertion 15 ns 1 tdrive_pd# t drpd differential output enable after pd# de-assertion 300 us 1 tdrive_cpu t drsrc cpu output enable after cpu_stop# de-assertion 10 ns 1 tfall_pd# t fall 5 ns 1 trise_pd# t rise 5 ns 1 fall/rise time of pd#, pci_stop# and cpu_stop# inputs ac electrical characteristics - low power different ial outputs parameter symbol conditions min max units notes rising edge slew rate t slr differential measurement 2.5 8 v/ns 1,2 falling edge slew rate t flr differential measurement 2.5 8 v/ns 1,2 slew rate variation t slvar single-ended measurement 20 % 1 maximum output voltage v high includes overshoot 1150 mv 1 minimum output voltage v low includes undershoot -300 mv 1 differential voltage swing v swing differential measurement 300 mv 1 crossing point voltage v xabs single-ended measurement 300 550 mv 1,3,4 crossing point variation v xabsvar single-ended measurement 140 mv 1,3,5 duty cycle d cyc differential measurement 45 55 % 1 cpu jitter - cycle to cycle cpuj c2c differential measurement 85 ps 1 src0 jitter - cycle to cycle srcj c2c differential measurement 125 ps 1 src[11:1] jitter - cycle to cycle srcj c2c differential measurement 85 ps 1 sata jitter - cycle to cycle sataj c2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotj c2c differential measurement 250 ps 1 cpu[1:0] skew cpu skew10 differential measurement 100 ps 1 cpu[2_itp:0] skew cpu skew20 differential measurement 150 ps 1 src[11,7,4,2,0] skew src skew differential measurement ps 1 src[10,9,8,6,3] skew src skew differential measurement 3 ns 1 0 nominal
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 12 intentional pci clock to clock delay 200 ps nominal steps pci0 pci1pci2 pci3 pci4 pci_f5 1.0ns electrical characteristics - pciclk/pciclk_f parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 pp m 1,6 33.33mhz output nominal 30.00900 ns 6 33.33mhz output spread 30.15980 ns 6 absolute min/max period t abs 33.33mhz output nominal/spread 29.49100 30.65980 ns 6 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t skew v t = 1.5 v 250 ps 1 intentional pci-pci delay t delay v t = 1.5 v ps 1,9 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 500 ps 1 output low current i ol clock period t period 29.99100 output high current i oh 200 nominal electrical characteristics - usb48mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 p pm 1,6 clock period t period 48.00mhz output nominal 20.83125 20.83542 ns 6 absolute min/max period t abs 48.00mhz output nominal 20.48130 21.18540 ns 6 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 350 ps 1 output high current i oh output low current i ol
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 13 electrical characteristics - 27mhz_spread / 27mhz_n onspread parameter symbol conditions min typ max units notes -50 50 1,6 -15 15 6 clock period t period 27.000mhz output nominal 37.0365 37.0376 ns 6 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 edge rate t slewr/f rising/falling edge rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 t ltj long term (10us), vt = 1.5 v 800 ps 1 t jpk-pk v t = 1.5 v -200 200 ps 1 t jcyc-cyc v t = 1.5 v 200 ps 1 ppm output high current i oh output low current i ol long accuracy ppm see tperiod min-max values jitter electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 p pm 1,6 clock period t period 14.318mhz output nominal 69.8203 69.8622 ns 6 absolute min/max period t abs 14.318mhz output nominal 69.8203 70.86224 ns 6 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -33 -33 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 1000 ps 1
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 14 electrical characteristics - differential jitter pa rameters parameter symbol conditions min typ max units notes t jphasepll pcie gen 1 86 ps (p-p) 1,11 t jphaselo pcie gen 2 10khz < f < 1.5mhz 3 ps (rms) 1,11 t jphasehigh pcie gen 2 1.5mhz < f < nyquist (50mhz) 3.1 ps (rms) 1,11 *ta = -40 - 85c; supply voltage vdd = 3.3 v +/-5% , rs= 0 , cl = 2pf notes on electrical characteristics: 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around d ifferential zero 3 vxabs is defined as the voltage where clk = clk# 4 only applies to the differential rising edge (clk r ising and clk# falling) 6 all long term accuracy and clock period specificati ons are guaranteed assuming that refout is at 14.31 818mhz 10 at nominal voltage and temperature 11 see http://www.pcisig.com for complete specs 8 maximum input voltage is not to exceed maximum vdd 9 see pci clock-to-clock delay figure jitter, phase 5 defined as the total variation of all crossing volt ages of clk rising and clk# falling. matching appli es to rising edge rate of clk and falling edge of clk#. it is measured using a +/-75m v window centered on the average cross point where clk meets clk#. the average cross point is used to calculate the voltag e thresholds the oscilloscope is to use for the edg e rate calculations. 7 operation under these conditions is neither implied , nor guaranteed.
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 15 fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz usb mhz dot mhz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 1 1 1 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common outpu t parameters table for correct values. table 1: cpu frequency select table 96.00 100.00 33.33 14.318 48.00 reserved 27fix/lcdt/srct_lr1/se1 27ss/lcdc/srcc_lr1/se2 spread mhz mhz % 0 0 0 0 0 0 0 0 0 1 100.00 100.00 srcclk1 from src_main 0 0 0 1 0 100.00 100.00 -0.50% lcdclk from pll1 0 0 0 1 1 100.00 100.00 -1% lcdclk from pll1 0 0 1 0 0 100.00 100.00 -1.50% lcdclk from pll1 0 0 1 0 1 100.00 100.00 +/-0.25% lcdclk from pll1 0 0 1 1 0 100.00 100.00 +/-0.5% lcdclk from pll1 0 0 1 1 1 n/a n/a n/a n/a 0 1 0 0 0 24.576 24.576 none 24.576mhz on se1 and se2 0 1 0 0 1 24.576 98.304 none 24.576mhz on se1, 98.304mhz on se2 0 1 0 1 0 98.304 98.304 none 98.304mhz on se1 and se2 0 1 0 1 1 27.000 27.000 none 27mhz on se1 and se2 0 1 1 0 0 25.000 25.000 none 25mhz on se1 and se2 0 1 1 0 1 n/a 0 1 1 1 0 n/a n/a n/a n/a 0 1 1 1 1 n/a n/a n/a n/a 1 0 0 0 0 n/a n/a n/a 1 0 0 0 1 n/a n/a n/a 1 0 0 1 0 27mhz_nonss 27mhz_ss -0.5% 1 0 0 1 1 27mhz_nonss 27mhz_ss -1% 1 0 1 0 0 27mhz_nonss 27mhz_ss -1.5% 1 0 1 0 1 27mhz_nonss 27mhz_ss -2% 1 0 1 1 0 27mhz_nonss 27mhz_ss -0.75% 1 0 1 1 1 27mhz_nonss 27mhz_ss -1.25% 1 1 0 0 0 27mhz_nonss 27mhz_ss -1.75% 1 1 0 0 1 27mhz_nonss 27mhz_ss +-0.5% 1 1 0 1 0 27mhz_nonss 27mhz_ss +-0.75% 1 1 0 1 1 n/a n/a 1 1 1 0 0 n/a n/a 1 1 1 0 1 n/a n/a 1 1 1 1 0 n/a n/a 1 1 1 1 1 n/a n/a note: mode 00000 ~ 00110 on table 2 only applies w hen src_main source is from pll5. pll1 & pll2 disabled b1b1 b1b4 b1b3 b1b2 table 2: 27fix/lcdt/srct_lr1/se1, 27ss/lcdc/srcc_lr 1/se2 configuration 27_sel comment
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 16 table 3: io_vout select table b9b2 b9b1 b9b0 io_vout 0 0 0 0.3v 0 0 1 0.4v 0 1 0 0.5v 0 1 1 0.6v 1 0 0 0.7v 1 0 1 0.8v 1 1 0 0.9v 1 1 1 1.0v table 4: device id table 0 0 0 0 64 pin mlf 0 0 0 1 64 pin tssop 0 0 1 0 reserved 0 0 1 1 reserved 0 1 0 0 reserved 0 1 0 1 reserved 0 1 1 0 reserved 0 1 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved comment b8b7 b8b6 b8b5 b8b4
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 17 pd# cpu_stop# pci_stop# pereq# smbus register oe cpu0 cpu0# cpu1 cpu1# cpu2 cpu2# 1 1 1 x enable running running running running running running 0 x x x enable low/20k low low/20k low low/20k low 1 0 x x enable high low high low high low 1 x x x disable low/20k low low/20k low low/20k low low/20k low running running low/20k low cpu power management table m1 pciex, lcd power management table pd# cpu_stop# pci_stop# pereq# smbus register oe pciet pciec pciet pciec lcd lcd # lcd lcd # sata sata# sata sata# 1 x 1 0 enable running running running running running running running running running running running running 0 x x x enable low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low 1 x 0 0 enable running running high low running running high low running running high low 1 x x 1 enable running running low/20k low running running running running running running running running 1 x x x disable low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low free-run stoppable m1 free-run stoppable free-run stoppable dot, sata power management table pd# cpu_stop# pci_stop# pereq# smbus register oe dot dot# 1 x 1 x enable running running 0 x x x enable low/20k low 1 x 0 x enable running running 1 x x x enable running running 1 x x x disable low/20k low low/20k low m1 pd# cpu_stop# pci_stop# pereq# smbus register oe pcif/pci pcif/pci usb48 ref 27m se free-run stoppable 1 x 1 x enable running running running running running running 0 x x x enable low low low low low low 1 x 0 x enable running low running running running running 1 x x x disable low low low low low low low low low low low low singled-ended power management table m1
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 18 general smbus serial interface information for the ICS9ERS3165 ho w to write: ? controller (host) sends a star t bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) star ts sending byte n thr ough byte n + x -1 ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read:? controller (host) will send star t bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the begining bytelocation = n ? ics clock will acknowledge ? controller (host) will send a separ ate star t bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge p stop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 19 byte 0 fs readback & pll selection register bit name description type 0 1 default 7 fslc cpu freq. sel. bit (most significant) r latch 6 fslb cpu freq. sel. bit r latch 5 fsla cpu freq. sel. bit (least significant) r latch 4 iamt_en set via smbus or dynamically by ck505 if de tects dynamic m1 r legacy mode iamt enabled iamt power on status 3 reserved reserved rw 0 2 src_main_sel select source for src main rw src main = pll5 src main = pll2 0 1 sata_sel select source for sata clock rw sata = src_main sata = pll3 0 0 pd_restore 1 = on power down de-assert return to last known st ate 0 = clear all smbus configurations as if cold power -on and go to latches open state this bit is ignored and treated at '1' if device is in iamt mode. rw configuration not saved configuration saved 1 byte 1 pll1 quick config register note 1 : when 27_select pin = 0, b1b7 pwd = 1; whe n 27_select pin = 1, pwd = 0 bit name description type 0 1 default 7 src0_sel select src0 or dot96 rw src0 dot96 note 1 6 pll5_ssc_sel select 0.5% down or center ssc rw down spread center spread 0 5 pll2_ssc sel select 0.5% center or down ssc rw down center 0 4 pll1_cf3 pll1 quick config bit 3 rw 0 3 pll1_cf2 pll1 quick config bit 2 rw 0 2 pll1_cf1 pll1 quick config bit 1 rw 1 1 pll1_cf0 pll1 quick config bit 0 rw 0 0 pci_sel pci_sel rw pci from pll5 pci from src_main 1 byte 2 single ended output enable register bit name description type 0 1 default 7 ref_oe output enable for ref rw output disabled output enabled 1 6 usb_oe output enable for usb rw output disabled output enabled 1 5 pcif5_oe output enable for pci5 rw output disabled output enabled 1 4 pci4_oe output enable for pci4 rw output disabled output enabled 1 3 pci3_oe output enable for pci3 rw output disabled output enabled 1 2 pci2_oe output enable for pci2 rw output disabled output enabled 1 1 pci1_oe output enable for pci1 rw output disabled output enabled 1 0 pci0_oe output enable for pci0 rw output disabled output enabl ed 1 byte 3 src output enable register bit name description type 0 1 default 7 src11_oe output enable for src11 rw output disabled output enabled 1 6 src10_oe output enable for src10 rw output disabled output enabled 1 5 src9_oe output enable for src9 rw output disabled output enabled 1 4 src8/itp_oe output enable for src8 or itp rw output disabled output enabled 1 3 src7_oe output enable for src7 rw output disabled output enabled 1 2 src6_oe output enable for src6 rw output disabled output enabled 1 1 reserved reserved rw - - 1 0 src4_oe output enable for src4 rw output disabled outp ut enabled 1 byte 4 src/cpu/dot output enable & spread spectrum disable register bit name description type 0 1 default 7 src3_oe output enable for src3 rw output disabled output enabled 1 6 sata/src2_oe output enable for sata/src2 rw output disabled output enabled 1 5 src1_oe output enable for src1 rw output disabled output enabled 1 4 src0/dot96_oe output enable for src0/dot96 rw output disabled output enabled 1 3 cpu1_oe output enable for cpu1 rw output disabled output enabled 1 2 cpu0_oe output enable for cpu0 rw output disabled output enabled 1 1 pll5_ssc_on enable pll5's spread modulation rw spread disabled spread enabled 1 0 pll2_ssc_on enable pll2's spread modulation rw spread disabled spread enabled 1 byte 5 clock request enable/configuration register bit name description type 0 1 default 7 cr#_a_en enable cr#_a (clk req) for src0 or src2 rw disable cr#_a enable cr#_a 0 6 cr#_a_sel sets cr#_a to control either src0 or src2 rw cr#_a -> src0 cr#_a -> src2 0 5 cr#_b_en enable cr#_b (clk req) for src1 or src4 rw disable cr#_b enable cr#_b 0 4 cr#_b_sel sets cr#_b to control either src1 or src4 rw cr#_b -> src1 cr#_b -> src4 0 3 cr#_c_en enable cr#_c (clk req) for src0 or src2 rw disable cr#_c enable cr#_c 0 2 cr#_c_sel sets cr#_c to control either src0 or src2 rw cr#_c -> src0 cr#_c -> src2 0 1 cr#_d_en enable cr#_d (clk req) for src1 or src4 rw disable cr#_d enable cr#_d 0 0 cr#_d_sel sets cr#_d to control either src1 or src4 rw cr#_d -> src1 cr#_d -> src4 0 see table 1 : cpu frequency select table see table 2: pin 27fix/lcdt/srct_lr1/se1, 27ss/lcdc/srcc_lr1/se2 configuration only applies if byte 0, bit 2 = 0.
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 20 byte 6 clock request enable/configuration register bit name description type 0 1 default 7 cr#_e_en enable cr#_e (clk req) for src6 rw disable cr#_e enable cr#_e 0 6 cr#_f_en enable cr#_f (clk req) for src8 rw disable cr#_f enable cr#_f 0 5 cr#_g_en enable cr#_g (clk req) for src9 rw disable cr#_g enable cr#_g 0 4 cr#_h_en enable cr#_h (clk req) for src10 rw disable cr#_h enable cr#_h 0 3 reserved reserved rw - - 0 2 reserved reserved rw - - 0 1 lcd/src1_stp_crtl ? if set, lcd_ss/src1 stops with pci_stop# rw free ru nning stops with pci_stop# assertion 0 0 src0_stp_crtl if set, src0 stop with pci_stop# rw fre e running stops with pci_stop# assertion 0 byte 7 vendor id/ revision id register bit name description type 0 1 default 7 rev code bit 3 r 0 6 rev code bit 2 r 0 5 rev code bit 1 r 0 4 rev code bit 0 r 1 3 vendor id bit 3 r 0 2 vendor id bit 2 r 0 1 vendor id bit 1 r 0 0 vendor id bit 0 r 1 byte 8 device id & output enable register bit name description type 0 1 default (tssop) default (mlf) 7 device_id3 r 0 0 6 device_id2 r 0 0 5 device_id1 r 0 0 4 device_id0 r 1 0 3 reserved reserved rw - - 0 0 2 reserved reserved rw - - 0 0 1 27mhz_nonss/se1_oe output enable for se1 rw disabled enabled 1 1 0 27mhz_ss/se2_oe output enable for se2 rw disabled enabled 1 1 byte 9 test and output control register bit name description type 0 1 default 7 pcif5 stop en allows control of pcif5 with assertio n of pci_stop# rw free running stops with pci_stop# assertion 0 6 tme_readback truested mode enable (tme) strap status r normal operation no overclocking tme latch 5 reserved reserved rw - - 1 4 test mode select allows test select, ignores ref/fsc/testsel rw outputs hi-z outputs = ref/n 0 3 test mode entry allows entry into test mode, ignores fsb/testmode rw normal operation test mode 0 2 cpu io_vout2 cpu io output voltage select (most significant bit) rw 1 1 cpu io_vout1 cpu io output voltage select rw 0 0 cpu io_vout0 cpu io output voltage select (least si gnificant bit) rw 1 byte 10 output control register bit name description type 0 1 default 7 27_sel latch readback readback of 27_select latch r dot96/ lcd_ss /se src0/ 27mhz 27_sel latch 6 pci4 stop en allows control of pci4 with assertion of pci_stop# rw free running stops with pci_stop# assertion 1 5 pci3 stop en allows control of pci3 with assertion of pci_stop# rw free running stops with pci_stop# assertion 1 4 pci2 stop en allows control of pci2 with assertion of pci_stop# rw free running stops with pci_stop# assertion 1 3 pci1 stop en allows control of pci1 with assertion of pci_stop# rw free running stops with pci_stop# assertion 1 2 pci0 stop en allows control of pci0 with assertion of pci_stop# rw free running stops with pci_stop# assertion 1 1 cpu1 stop enable enables control of cpu1 with cpu_stop# rw free running stoppable 1 0 cpu0 stop enable enables control of cpu0 with cpu_s top# rw free running stoppable 1 byte 11 iamt/cpu2 control register bit name description type 0 1 default 7 reserved reserved rw - - 0 6 reserved reserved rw - - 0 5 reserved reserved rw - - 0 4 reserved reserved rw - - 0 3 cpu2_amt_en m1 mode clk enable, only if itp_en=1 rw disable enable 0 2 cpu1_amt_en m1 mode clk enable rw disable enable 1 1 reserved reserved rw - - 0 0 cpu2 stop enable enables control of cpu2 with cpu_s top# rw free running stoppable 1 revision id vendor specific vendor id ics is 0001, binary table of device identifier codes, used for differen tiating between ck505 package options, etc. see device id table 4 see table 3: v_io selection (default is 0.8v)
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 21 byte 12 byte count register bit name description type 0 1 default 7 reserved reserved rw - - 0 6 reserved reserved rw - - 0 5 bc5 rw - - 0 4 bc4 rw - - 0 3 bc3 rw - - 1 2 bc2 rw - - 1 1 bc1 rw - - 0 0 bc0 rw - - 1 byte 13 single ended output slew rate control regis ter bit name description rw 0 1 default 7 ref rw 00 = hi-z 01 = 1.4 v/ns 0 6 ref rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 5 27m_fix rw 00 = hi-z 01 = 1.4 v/ns 0 4 27m_fix rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 3 27m_ss rw 00 = hi-z 01 = 1.4 v/ns 0 2 27m_ss rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 1 reserved reserved rw - - 0 0 reserved reserved rw - - 0 byte 14 reserved bit name description type 0 1 default 7 reserved reserved rw - - x 6 reserved reserved rw - - x 5 reserved reserved rw - - x 4 reserved reserved rw - - x 3 reserved reserved rw - - x 2 reserved reserved rw - - x 1 reserved reserved rw - - x 0 reserved reserved rw - - x byte 15 reserved bit name description type 0 1 default 7 reserved reserved rw - - x 6 reserved reserved rw - - x 5 reserved reserved rw - - x 4 reserved reserved rw - - x 3 reserved reserved rw - - x 2 reserved reserved rw - - x 1 reserved reserved rw - - x 0 reserved reserved rw - - x byte 16 reserved bit name description type 0 1 default 7 reserved reserved rw - - x 6 reserved reserved rw - - x 5 reserved reserved rw - - x 4 reserved reserved rw - - x 3 reserved reserved rw - - x 2 reserved reserved rw - - x 1 reserved reserved rw - - x 0 reserved reserved rw - - x byte 17 src output control register bit name description rw 0 1 default 7 sata/src2_stp_crtl if set, sata/src2 stops with pci_ stop# rw free running stops with pci_stop# assertion 0 6 src3_stp_crtl if set, src3 stops with pci_stop# rw fre e running stops with pci_stop# assertion 0 5 src4_stp_crtl if set, src4 stops with pci_stop# rw fre e running stops with pci_stop# assertion 0 4 src6_stp_crtl if set, src6 stops with pci_stop# rw fre e running stops with pci_stop# assertion 0 3 src7_stp_crtl if set, src7 stops with pci_stop# rw fre e running stops with pci_stop# assertion 0 2 reserved reserved rw - - 0 1 src8_stp_crtl if set, src8 stops with pci_stop# rw fre e running stops with pci_stop# assertion 0 0 src9_stp_crtl if set, src9 stops with pci_stop# rw fre e running stops with pci_stop# assertion 0 read back byte count register, max bytes = 32 slew rate control slew rate control slew rate control
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 22 byte 18 differential output control register bit name description rw 0 1 default 7 src10_stp_crtl if set, src10 stops with pci_stop# rw f ree running stops with pci_stop# assertion 0 6 src11_stp_crtl if set, src11 stops with pci_stop# rw f ree running stops with pci_stop# assertion 0 5 src/cpuitp_src8 io_vout2 src & cpuitp_src8 io output voltage select (most si gnificant bit) rw 1 4 src/cpuitp_src8 io_vout1 src io & cpuitp_src8 output voltage select rw 0 3 src/cpuitp_src8 io_vout0 src & cpuitp_src8 io output voltage select (least significant bit) rw 1 2 sata/src2 io_vout2 sata_src2 io output voltage select (most significan t bit) rw 1 1 sata/src2 io_vout1 sata_src2 io output voltage select rw 0 0 sata/src2 io_vout0 sata_src2 io output voltage selec t (least significant bit) rw 1 byte 19 differential output control register bit name description rw 0 1 default 7 lcd_ss (src1) io_vout2 lcd_ss io output voltage select (most significant b it) rw 1 6 lcd_ss (src1) io_vout1 lcd_ss io output voltage select rw 0 5 lcd_ss (src1) io_vout0 lcd_ss io output voltage select (least significant bit) rw 1 4 src0/dot96 io_vout2 src0_dot96 io output voltage sel ect (most significant bit) rw 1 3 src0/dot96 io_vout1 src0_dot96 io output voltage select rw 0 2 src0/dot96 io_vout0 src0_dot96 io output voltage sel ect (least significant bit) rw 1 1 reserved reserved rw - - 0 0 reserved reserved rw - - 0 byte 20 single ended slew rate control register bit name description type 0 1 default 7 48mhz rw 00 = hi-z 01 = 1.4 v/ns 0 6 48mhz rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 5 pcif5 rw 00 = hi-z 01 = 1.4 v/ns 0 4 pcif5 rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 3 pci4 rw 00 = hi-z 01 = 1.4 v/ns 0 2 pci4 rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 1 pci3 rw 00 = hi-z 01 = 1.4 v/ns 0 0 pci3 rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 byte 21 single ended slew rate & m/n enable control register bit name description type 0 1 default 7 pci2 rw 00 = hi-z 01 = 1.4 v/ns 0 6 pci2 rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 5 pci1 rw 00 = hi-z 01 = 1.4 v/ns 0 4 pci1 rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 3 pci0 rw 00 = hi-z 01 = 1.4 v/ns 0 2 pci0 rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 1 reserved reserved rw - - 0 0 reserved reserved rw - - 0 see table 3: v_io selection (default is 0.8v) slew rate control slew rate control slew rate control see table 3: v_io selection (default is 0.8v) see table 3: v_io selection (default is 0.8v) see table 3: v_io selection (default is 0.8v) slew rate control slew rate control slew rate control slew rate control
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 23 test clarification table comments fslc/ test_sel hw pin fslb/ test_mode hw pin test entry bit b9b3 ref/n or hi-z b9b4 output <2.0v x 0 0 normal >2.0v 0 x 0 hi-z >2.0v 0 x 1 ref/n >2.0v 1 x 0 ref/n >2.0v 1 x 1 ref/n <2.0v x 1 0 hi-z <2.0v x 1 1 ref/n b9b3: 1= enter test mode, default = 0 (normal opera tion) b9b4: 1= ref/n, default = 0 (hi-z) hw sw ck_pwrg=1 w/ test_sel = 1 to enter test mode cycle power to disable test mode fslc./test_sel -->3-level latched input if ck_pwrg=1 w/ v>2.0v then use test_sel if ck_pwrg=1 w/ v<2.0v then use fslc fslb/test_mode -->low vth input test_mode is a real time input if test_sel hw pin is 0 after ck_pwrg=1, test mode can be invoked through b9b3. if test mode is invoked by b9b3, only b9b4 is used to select hi-z or ref/n fslb/test_mode pin is not used. cycle power to disable test mode, one shot control
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 24
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 25
idt ? embedded 64-pin industrial t emperature range ck505 comp atible clock 1613c?02/08/12 ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 26 ordering information part/order number shipping packaging package temperatu re 9ers3165bkilf tubes 64-pin mlf -40 to +85 c 9ers3165bkilft tape and reel 64-pin mlf -40 to +85 c 9ers3165bgilf tubes 64-pin tssop -40 to +85 c 9ers3165bgilft tape and reel 64-pin tssop -40 to +85 c parts that are ordered w ith a ?lf? suffix to the pa rt num ber are the pb-free configuration and are roh s com pliant. due to package size constraints, actual top-side m a rking m ay differ from the full orderable part num be r. indexarea 1 2 n d e1 e a seating plane a1 a a2 e - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 de e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 64 16.90 17.10 .665 .673 10-0039 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (2 0 mil) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153
ICS9ERS3165 embedded 64-pin industrial t emperature range ck505 comp atible clock 27 innovate with idt and accelerate your future networks. cont act: www .idt .com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for t ech support 408-284-6578 pcclockhelp@id t.com corporate headquarters integrated device t echnology , inc. 6024 silver creek v alley road san jose, ca 95138 united s t ates 800 345 7015 +408 284 8200 (out side u.s.) asia pacific and jap an integrated device t echnology singapore (1997) pte. lt d. reg. no. 199707558g 435 orchard road #20-03 w isma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett w ood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2009 integrated device t echnology , inc. all right s reserved. product specifications subject to change without notice. idt , ics, and the idt logo are trademarks of integrated device t echnology , inc. accelerated thinking is a service mark of integrated device t echnology , inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision history rev. issue date description page # 0.1 04/29/09 initial release - 0.2 04/30/09 updates to electrical tables. various 0.3 06/29/09 updated tssop/mlf pinout and description s, table 2, and byte 1. various a 08/19/09 released to final b 01/25/10 updated document template c 02/08/12 updated mlf package drawing and footrint

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